FLEXIOSRC=00, PLLFLLSEL=00, LPI2C0SRC=00, RTCCLKOUTSEL=0, LPI2C1SRC=00, LPUARTSRC=00, TRACECLKSEL=0, USBSRC=0, TPMSRC=00
System Options Register 2
| LPI2C1SRC | LPI2C1 source 0 (00): Clock disabled 1 (01): MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL]. 2 (10): OSCERCLK clock 3 (11): MCGIRCLK clock |
| RTCCLKOUTSEL | RTC clock out select 0 (0): RTC 1 Hz clock is output on the RTC_CLKOUT pin. 1 (1): RTC 32.768kHz clock is output on the RTC_CLKOUT pin. |
| CLKOUTSEL | CLKOUT select 2 (010): Flash clock 3 (011): LPO clock (1 kHz) 4 (100): MCGIRCLK 5 (101): RTC 32.768kHz clock 6 (110): OSCERCLK0 7 (111): IRC 48 MHz clock |
| LPI2C0SRC | LPI2C0 source 0 (00): Clock disabled 1 (01): MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL]. 2 (10): OSCERCLK clock 3 (11): MCGIRCLK clock |
| TRACECLKSEL | Debug trace clock select 0 (0): MCGOUTCLK 1 (1): Core/system clock |
| PLLFLLSEL | PLL/FLL clock select 0 (00): MCGFLLCLK clock 1 (01): MCGPLLCLK clock 3 (11): IRC48 MHz clock |
| USBSRC | USB clock source select 0 (0): External bypass clock (USB_CLKIN). 1 (1): MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by SIM_CLKDIV2[USBFRAC, USBDIV]. |
| FLEXIOSRC | FlexIO Module Clock Source Select 0 (00): I2S0_MCLK or System clock, selected via SIM_MISCCTRL[FlEXIOS0] 1 (01): MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL]. 2 (10): OSCERCLK clock 3 (11): MCGIRCLK clock |
| TPMSRC | TPM clock source select 0 (00): Clock disabled 1 (01): MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL]. 2 (10): OSCERCLK clock 3 (11): MCGIRCLK clock |
| LPUARTSRC | LPUART clock source select 0 (00): Clock disabled 1 (01): MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL]. 2 (10): OSCERCLK clock 3 (11): MCGIRCLK clock |